Divider Solve exercise 12.7 using SystemVerilog instead of VHDL.
Exercise 7 in Chapter 12
Divider This exercise concerns the sequential divider of figure 11.13.
(a) How many DFFs are needed to build it for N = 32 bits and sequential encoding?
(b) Implement it using VHDL. Check whether the number of DFFs inferred by the compiler matches your estimate.
(c) Recompile the code for N = 4 and simulate it using the same stimuli of figure 11.13a, checking whether the same results are obtained here.
