For this project, your ISA should be completed with a python simulator to execute the 2 programs. Again, your ISA should feature 8-bit instructions (including 1 parity bit) and 16-bit data (registers and memory), which you will optimize for two programs (ME - "Modular Exponentiation", and BMC - "Best Match Count").
credit: multi-cycle CPU implementation of your ISA (supported by the simulator for correct DIC counting, and HW schematics including control unit FSM. Consider breaking the process of instruction according to the IF / ID-RR / ALU / MEM / WB stages.
Submission components:
Include the following 7 files in your Bb submission:
- p3_group_x_report.pdf: a self-contain PDF report writeup
- p3_group_x_sim.py: Python simulator for your ISA
- p3_group_x_dmem_A.txt: result data memory pattern A
- p3_group_x_dmem_B.txt: result data memory pattern B
- p3_group_x_dmem_C.txt: result data memory pattern C
- p3_group_x_dmem_D.txt: result data memory pattern D
- p3_group_x_p1_imem.txt: machine code for P1 (EM)
- p3_group_x_p2_imem.txt: machine code for P2 (BMC)
- (optional) p3_group_x_p0_imem.txt: machine code for P0 (your choice)
Part A) ISA intro - a recap of your ISA design
1. Introduction. Name of the architecture, overall philosophy, specific goals strived for and achieved.
2. Instruction list. Give all the instructions, their formats, opcodes, and an example.
3. Register design. List of the supported registers and any special designs.
4. Control flow (branches). Design of conditional and unconditional branches: target addresses calculation, maximum branch distance supported, and other unique designs of your ISA's branch instructions.
5. Data memory addressing modes. Mechanisms of your load / store instructions and their corresponding machine code.
Part B) Answers to questions
1. What are the most significant advantages of your ISA (with regard to the two programs, hardware implementation, ease of programming, etc)? What are the main limitations? What are the main compromises that you have done to make things work, rather than perfecting everything?
2. What have you done towards the goals of low DIC and HW simplification? What could have been done differently to better optimize for each of the two goals, if to start over?
3. Reflect on this project(1-3) experience:
a. What did you learn from this project? What was the best / worst thing about it?
b. What advice would you give to someone taking this project in a future semester?
c. How would you describe the value of this project experience in a job interview?
Part C) Simulation results
1. Execution results: data mem[0] - data mem[5], and DIC for each case
a. for the two given sample data memory pattern version A and B (see Appendix)
b. two other data sets C and D (of your choice, to present some meaningful features)
2. Execution process of the two target programs: show the (important, illustrative parts of the) python screen output during the process of running P1 and P2, based on various data memory patterns (A, B, C, D), so that it is evident:
a. every instruction is illustrated for its correct simulation.
b. every program on each pattern is achieving the correct results.
3. If your simulation cannot correctly achieve both P1 and P2, include a simpler program P0 to illustrate a successful simulation process / outcome.
Part D) ISA package
1. Algorithms (in assembly code) of the two programs (and P0 if needed). Make sure your assembly format is either obvious or well described, and that the code is well commented.
2. (Instr mem) Machine Code for P1 and P2 (and P0 if needed).
3. (Data mem) Pattern C and D of your own design to showcase your programs.
4. Python simulator code.
5. HW schematics
a. ALU schematic. A hierarchical sketch of your Arithmetic Logic Unit which implements whatever computation that your ISA instructions use.
b. CPU Datapath design. A schematic including your register file, ALU, PC logic, and memory components (see textbook ch 7.3.1).
c. Control logic design. Decoder truth-table (or FSM for multi-cycle implementation) indicating how each control signal is generated from an instruction.
Attachment:- pattern.rar