1. What is the clock cycle time with and without this improvement?
2. What is the speedup achieved by adding this improvement?
3. Compare the cost/performance ratio with and without this improvement.
4. Problems in this exercise assume that logic blocks needed to implement a processor's datapath have the following latencies:
![1989_3f24cdc7-e24e-49cb-a505-f2bec41b0b44.png](https://secure.tutorsglobe.com/CMSImages/1989_3f24cdc7-e24e-49cb-a505-f2bec41b0b44.png)