Assignment:
Using negative edge triggered J-K flip-flops, design a 3-bit synchronous sequence generator to generate the following sequence:
0,1,3,6,0....
1. Draw up a table showing the input requirements on the J & K terminals for the four possible changes of state at the output. The table should be headed: PRESENT Q, NEXT Q, INPUTS J,K.
2. Draw up a state table for the required sequence showing:
PRESENT OUTPUT STATE,NEXT OUTPUT STATE, JK INPUTS
For each state change. Treat the states 2,4,5&7as "don't care" states.
3. Using karnaugh maps for Jc Kc,Jb Kb and Ja Ka derive the minimised expressions required for each.
4. Draw a block diagram of your solution.
5. Describe what would happen if the circuit were to take up any of the "don't care" states at switch-on. Would there be a problem ? If so, how would you overcome it? Show how you derived your answer.