Prepare a schematic design of the five-stage multiply

Question

Problem

Design a binary integer multiply pipeline with five stages. The first stage is for partial product generation. The last stage is a 36-bit carry-lookahead adder. The middle three stages are made of 16 carry-save adders (CSAs) of appropriate lengths.

(a) Prepare a schematic design of the five-stage multiply pipeline. All line widths and inter-stage connections must be shown.

(b) Determine the maximal clod rate of the pipeline if the stage delays are τ₁ = τ₂ = τ₃ = τ₄ = 9 ns, τ₅ = 4ns, and the latch delay is 1 ns.

(c) What is the maximal throughput of this pipeline in terms of the number of 36-bit results generated per second?