1) Sketch the V-I characteristics for nmos enhancement and the depletion mode transistor.
2) Explain the static power consumption in the CMOS inverter?
3) Explain the chief drawbacks of an inverter with resistive load.
4) Implement the nand gate by using nmos pass transistor logic.
5) Explain the difference between the registers and latches?
6) Explain the basic principle in the dynamic logic?
7) Specify some of the objectives of K-L algorithm?
8) Specify the steps included for the constructive partitioning algorithm.
9) Explain the Hooke’s law in force directed placement method.
10) Explain the several classifications in the floor planning algorithm?