A 4 × 4 array multiplier (Figure 4-29) is to be implemented using an FPGA.
(a) Partition the logic so that it fits in a minimum number of Figure 6-1(a) logic blocks. Draw loops around each set of components that will fit in a single logic block. Determine the total number of four-input LUTs required.
(b) Repeat part (a), except assume that carry chain logic is available.
