Parallel fetch-execute pipelines for superscalar


For problems 7 through 9, consider a CPU that implements four parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in Advanced Systems Concepts, i.e.:
• a one clock cycle fetch
• a one clock cycle decode
• a two clock cycle execute
and a 60 instruction sequence:
7. (12 points) Νo pipelining would require _____ clock cycles: 

8. (12 points) A scalar pipeline would require _____ clock cycles:

9. (12 points) A superscalar pipeline with four parallel units would require ______ clock cycles:

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Basic Computer Science: Parallel fetch-execute pipelines for superscalar
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