Consider a pipelined than can issue up to one instruction per cycle, but fewer may be issued because of pipeline hazards, multi-cycle latency ALU operations and memory access to slower memories. It has a clock speed of 3.2Ghz. It executes a program with 1.8 billion instructions in 1.4 seconds, devoting 90% of the CPU's time to the program. What was the actual achieved issue rate of instructions per cycle?