Simulate the latch circuit of Figure 7-82(b) under the conditions described in the text on page 601. You may write a VHDL or Verilog structural model in which each gate has a delay of 1 ns, or draw the waveforms by hand, again assuming a delay of 1 ns per gate. Does the circuit behave as claimed in the text? Increase the delay of the inverter in the circuit to 3 ns, repeat the simulation, and explain the results. What would you expect to happen in the real circuit?
