1. A cache designer wants to increase the size of a 4 KiB virtually indexed, physically tagged cache. Given the page size shown above, is it possible to make a 16 KiB direct-mapped cache, assuming 2 words per block? How would the designer increase the data size of the cache?
2. In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system.
