Assignment -
Consider a multiprocessor with the initial state of the cache and memory as shown below. A processor can execute operations of the form:
P#: [)
where P# designates the CPU (e.g., P0), is the CPU operation (e.g., read or write), denotes the memory address, and indicates the new word to be assigned on a write operation. Assume the caches are direct mapped.
![143_figure.png](https://secure.tutorsglobe.com/CMSImages/143_figure.png)
1. Are all caches coherent? Justify your answer.
2. Show the states of the blocks that are changed and the value returned by operation P3: read 128. Use a cache coherence protocol to make caches coherent.
3. In the state after the above operation, show the states of all the blocks that are changed by operation P0: write 128 <0040>. Use a cache coherence protocol to make caches coherent.