In the diagram above, the inverter and the AND-gates labeled 1 and 2 have delays of 9, 10 and 12 nanoseconds, respectively. Wire delays are negligible. For certain values of a and c, together with a certain transition of b, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of the glitch is
A. 7ns
B. 9fts
C. llns
D. 13ns
E. 31ns