A non-pipelined processor X has a clock rate of 25 MHz and an average CPI (cycle per instruction) of 4. Processor Y, an improved successor of X, is designed with a 5- stage linear instruction pipeline. However, due to latch delay and clock skew effects, the clock rate of Y is only 20 MHz. (a) If a program containing 100 instructions is executed on both processors, what is the speedup of processor Y compared with that of processor X? (b) Calculate the MIPS (Millions of Instructions Per Second) rating for each processor during the execution of this particular program