Problem
1. How would you program the PMMU's TC register to implement a two-level page system with a page size of 8 Kbytes and a 30-bit logical address? There is no unique answer to this question and you must state your assumptions.
2. Why can some of the PMMU's cache's page descriptors be locked and kept in the ATC permanently? What are the dangers of locking these descriptors, and how does the PMMU try to protect you?
The response should include a reference list. Double-space, using Times New Roman 12 pnt font, one-inch margins, and APA style of writing and citations.