Consider a DRAM cell like that illustrated in Fig. 15.20.
(a) Estimate the storage time of a cell with the following parameters:
(b) The time you found in part a should have been rather substantial, and actual RAM storage times are much shorter because of additional leakage paths. One such path corresponds to excess diode current around the perimeter of the junction at the oxide interface. How will your answer change if there is an additional current of 10-10 A per centimeter of penmeter?
(c) Another source of leakage is subthreshold conduction, which is current flow between the source and drain of a MOSFET that occurs even though the device is cutoff. (We modeled this as RSD in Fig. 10.9.) Suppose that this current is 10-8 A per centimeter of gate width and that the gate is 5 pm wide. What is the storage time now?