Two-Loop FSM Figure 15.7 shows a two-loop FSM, with input x and output y. When in state 3 ... 6 the machine must transmit four bits from a z (3:0) array, starting with the MSB.
(a) How many flip-flops are needed to construct this FSM? Does your answer depend on the implementation approach (generic, seen in the previous chapters, or pointerbased, seen here)?
(b) Implement it using VHDL or SystemVerilog (pointer-based technique). Enter z in your code as a constant. After compilation, check whether the number of flip-flops inferred by the compiler matches your prediction.
(c) Show simulation results.
