Part -1:
1. How many bits are required to address a 16M x 32 main memory if
a) Main memory is byte addressable? ______
b) Main memory is word addressable? ______
2. Suppose that a 64M x 64 main memory is built using 8M x 32 RAM chips and memory is word addressable.
a) How many RAM chips are necessary? ______
b) How many RAM chips are needed for each memory word? _______
c) How many address bits are needed for each RAM chip? _______
d) How many address bits are needed for all memory? _______
3. A digital computer has a memory unit with 30 bits per word. The instruction set consists of 200 different operations. All instructions have an operation code part (opcode), and an address part (allowing for only one address). Each instruction is stored in one word of memory.
a) How many bits are needed for the opcode?
b) How many bits are left for the address part of the instruction?
c) What is the maximum allowable size for memory?
4. Write the following MARIE assembly language equivalent of the following machine language instructions
a) 0010 0000 1000 1111
b) 1001 1000 1011 0000
c) 0100 0011 0010 0001
d) 0101 0000 0000 0000
5. List the hexadecimal code for the following program.
Hex Address Label Instruction
100 Load A
101 Add One
102 Jump S1
103 S2, Add One
104 Store A
105 Halt
106 S1, Add A
107 Jump S2
108 A, HEX 0103
109 One, HEX 0001
Part -2:
1. Show how the value ASCII "MIRIAM" is stored in memory in Big Endian and in Little Endian format starting at location 100 hexadecimal. Assume that each memory location stores two ASCII characters.
|
Memory Location
|
Big Endian
|
Little Endian
|
|
100
|
|
|
|
101
|
|
|
|
102
|
|
|
2. For X = 1101 0100, show the result of the following independent operations (i.e. each instruction occurs with X starting at the value above:
a) Logical Shift left
b) Rotate right
c) Logical Shift right
d) Rotate left
e) Arithmetic Shift right
3 a. Convert the following formula from postfix (Reverse Polish Notation) to infix: ABCD-+/
3 b.. Convert the following formula from infix to postfix (Reverse Polish Notation): ( A + B) *(C - D) / E + F
4. Write code that performsthe computation in problem 3b X = ( A + B) *(C - D) / E + F
using CPUs that have the following instruction formats:
You may only use registers A through F, plus X and T.
Registers A through F may not be changed, i.e. their values are fixed.
Register T may be used as a temporary register, and Register X must contain the final answer.
4 a. Three-operand instructions
4 b. Stack instructions
5. Suppose we have the instruction Load 100.
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Address
|
Value
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R1
|
400
|
|
100
|
400
|
|
|
:
|
:
|
|
200
|
300
|
|
:
|
:
|
|
300
|
100
|
|
:
|
:
|
|
400
|
500
|
|
:
|
:
|
|
500
|
800
|
Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below:
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Mode
|
Value Loaded into AC
|
|
Immediate
|
|
|
Direct
|
|
|
Indirect
|
|
|
Indexed
|
|
Part -3:
1. Suppose a computer using direct mapped cache has 228 words of main memory and a cache of 512 blocks, where each cache block contains 8 words.
a. How many blocks of main memory are there?
b. What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields?
c. To which cache block will the memory reference 0081B2316 map?
2. Suppose a computer using fully associative cache has 226 words of main memory and a cache of 64 blocks, where each cache block contains 32 words.
a. How many blocks of main memory are there?
b. What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields?
c. To which cache block will the memory reference 02C47216 map?
3. Suppose a computer using set associative cache has 224 words of main memory and a cache of 128 blocks, and each cache block contains 16 words.
a. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields?
b. If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
4. Create a page translation table the meets the requirements of the virtual memory system shown below. Assume page (and frame) sizes of 10 with pages 0 through 3 in logical memory and frames 0 through 7 in physical memory.
Logical Memory Physical Memory
|
0
9
|
A
|
|
|
0
19
|
|
|
10
39
|
B
|
|
|
B
|
20
49
|
|
|
40
|
|
|
|
|
50
59
|
|
|
A
|
60
69
|
|
|
|
70
79
|
|
5. A computer system with 16K of memory, a Memory Management Unit with a page size of 2000, and the following page translation table (all numbers in hexadecimal):
|
Logical Address
|
Physical Start
|
|
0000
|
10000
|
|
2000
|
1F200
|
|
4000
|
2CC00
|
|
6000
|
22400
|
|
8000
|
30300
|
|
A000
|
41600
|
|
C000
|
81E00
|
|
E000
|
3F500
|
(Note: All additions and subtractions should be done in hexadecimal)
a. Indicate the physical memory locationcorresponding to logicaladdress 2210.
b. Indicate the logical address corresponding to physical memory location 41B55.
Part -4:
1. A 32-bit computer has two selector channels and one multiplexor channel. Each selector channel supports two magnetic disk and two magnetic tape units. The multiplexor channel has two line printers, two card readers, and ten VDT terminals connected to it. Assume the following transfer rates.
Disk drive 700 Kbytes/s
Magnetic tape drive 200 Kbytes
Line printer 6.6 Kbytes/s
Card Reader 1.2 Kbytes/s
VDT 1 Kbytes/s
Estimate the maximum aggregate I/O transfer rate in this system.
2. Given the following set of events, show which routines the CPU is executing for times 0 to 100 ns. Each handler routine (with its interrupt request) takes 20 ns to complete. The priority of the interrupts ranges from IRQ6 as the highest priority interrupt to IRQ0 as the lowest priority interrupt.
|
Time
|
Action
|
|
0 ns
|
Start of main program
|
|
10 ns
|
IRQ2
|
|
25 ns
|
IRQ5
|
|
40 ns
|
IRQ6
|
|
50 ns
|
IRQ1
|
Time Action
0 ns: Start of Main Program
10 ns: IRQ2
3. If an address bus needs to be able to address four devices, how many conductors will be required?
What if each of those devices also needs to be able to talk back to the I/O control device?
4. Define the terms seek time, rotational delay, and transfer time. Explain their relationship.
5. Suppose a disk drive has the following characteristics:
• 5 surfaces
• 512 tracks per surface
• 128 sectors per track
• 1024 bytes per sector
• Track-to-track seek time of 12 milliseconds
• Rotational speed of 1500 RPM
a) What is the capacity of the drive?
b) What is the access time?
5. What are the differences between multiprogramming, multiprocessing, and multithreading?
6. a) Why should assembly language be avoided for general application development?
Under what circumstances would you argue in favor of using assembly language code for developing an application program?
b) What are the advantages of using a compiled language over an interpreted one?
7. a) A RISC processor has 152 total registers, with 12 designated as global registers.
The 10 register windows each have 6 input registers and 6 output registers. How many local registers are in each register window set?
b) Indicate whether each of the following applies to CISC or RISC by placing either aC (for CISC) or an R (for RISC) in the blank.
1. ____ Instructions are interpreted by the microprogram.
2. ____ Fixed length, easily decoded instruction format.
3. ____ Highly specialized, infrequently used instructions.
4. ____ Use of overlapping register windows.
5. ____ Relatively few addressing modes.
8. Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the Section I B of "Advanced Systems Concepts", i.e.:
• a one clock cycle fetch
• a two clock cycle decode
• a two clock cycle execute and a 40 instruction sequence:
Show your work.
No pipelining would require _____ clock cycles:
Scalar pipeline would require _____ clock cycles:
Superscalar pipeline with two parallel units would require ______ clock cycles:
9.a) What is the essential characteristic of the superscalar approach to processor design?
b. What is the difference between the superscalar and superpipelined approaches?