How does multiplexer know which line to select?
This is managed by select lines. The select lines provide communication among different components of a computer. Now let's see how multiplexer also called as MUX. For simplicity we will take illustration of 4 ×1 MUX it implies that there are 4 input lines associated to 1 output line. For the sake of consistency we would call input line as I and output line as O and control line a selection line S or enable as E.
Please notice the way in that S0 and S1 are associated in circuit. To 'a' AND gate S0 and S1 are inputted in complement form which means 'a' gate will output I0 when both selection lines have a value 0 that means S¯0 = 1 and S¯1 = 1, which implies that S0= 0 and S1=0 and therefore first entry in truth table. Please note that at S0 = 0 and S1 = 0 AND gate 'b', 'c', 'd' will provide 0 output and when all these outputs will pass OR gate 'e' they will provide I0 as output for this case. Which is for S0=0 and S1=0 output becomes I0 which in another words can be called as 'For S0 = 0 and S1 = 0, I0 input line is triggered by MUX'. In the same way other entries in truth table are respective to logical nature of figure. Thus by having two control lines we can have a 4×1 MUX. To have 8×1 MUX we should have 3 control lines or with 3 control lines we can make 23 = 8 it implies that 8×1 MUX. In the same way with 'n' control lines we could have 2n×1 MUX. Another parameter that is principal in MUX design is a number of inputs to AND gate. These inputs are decided by voltage of gate that generally supports a maximum of 8 inputs to a gate.
Where can these devices used in computer? Multiplexers are used in digital circuits for data and organized signal routing. We have seen a theory where out of 'n' input lines 1 can be triggered so we have a reverse concept it implies that if we have one input line and data is passed to one of the possible 2n lines where 'n' denotes number of selection lines. This operation is known as Demultiplexing.