Assignment Task: Generate a schematic diagram for a D flip flop with clock enable. Use only standard gates like and, nand, xnor, etc. and a regular d-flip flop, that is a d-flip flop that does not have a clock enable. A d-flip flop with clock enable acts like a regular d-flip flop when the enable is high. When the enable is low, Q stays at it was on the last positive clock edge prior to the enable going low. Q does not get the value of d on a positive clock edge while the enable is low. NB: When the enable changes state it should not generate an additional clock edge or delay the time of a positive going clock edge.