Consider the operation of the differential sense amplifier of Fig. 16.20 following the rise of the sense control signal φs. Assume that a balanced differential signal of 0.1 V is established between the bit lines, each of which has a 1 pF capacitance. For VDD = 1.2 V, what value of Gm of each of the inverters in the amplifier is required to cause the outputs to reach 0.1VDD and 0.9VDD [from initial values of 0.5VDD - (0.1/2) and 0.5VDD + (0.1/2) volts, respectively] in 2 ns? If for the matched inverters, /Vt /=0.4 V and k1n = 4k1p = 500 μA/V2, what are the device widths required? If the input signal is 0.2 V, what does the amplifier response time become?
