Explaining signed and unsigned data types in vhdl

Question

Question 1) Write down the name of the various EDA (electronic design automation) tools available for synthesising and simulating digital systems.

Question 2) How do signed and unsigned data types in VHDL differ from each other?

Question 3) What do you mean by operator overloading?

Question 4) Describe: Signal, variable in detail.

Question 5) Write down the difference between a process and a function?

Question 6) Draw a dot diagram for a 2-input XOR using a ROM.

Question 7) What are the various sections of a VHDL code?

Question 8) How is programming and erasing of a UV-EPROM done?

Question 9) Explain the structure of a package.