Assignment: Digital Design and Computer Architecture
1. A processor has a 32 MB cache and a 64 bit data bus. What is the minimum width of the address bus needed to access the entire cache?
2. Explain why SRAM is less dense but faster than DRAM.
3. Give the machine code for the following assembly instructions (give your answer in hex format): beq $a0, $a1, L1 (the beq instruction is at address 0x00E20710 and the target L1 is at address 0x00E20724).
4. List the values on the control signals for the following instructions. The MIPS architecture and instruction formats studied in class are shown below for reference. Your answer needs to be 1, 0, or X for each signal (a 0 or 1 will not be accepted as a substitute for X).
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MemtoReg
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MemWrite
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Branch
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ALUSrc
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RegDst
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RegWrite
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sub r2, r5, r23
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beq r1, r3, L2
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sw r1, 36(r4)
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lw r3,100(r6)
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addi r2,r14,-24
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j L3
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