Question 1)a) Explain the fundamental issues in the hardware-software co-design.
b) Describe the ARM memory system and control logic with the diagram. Write the functions performed by the memory control logic.
Question 2)a) Explain the exceptions and exception handling in ARM processor in detail.
b) Write the MU0 register transfer level organization by adding index register. Give the control logic for the following instructions and describe the operation.
i) LDA S,X
ii) STA S,X
iii) INX
iv) DEX
Question 3)a) With respect to performance equation explain the various methods to speed up the processing. Give the major bottlenecks in performance improvement.
b) Describe the ARM7 debug architecture with the relevant diagrams. Write the advantages of using JTAG port in the debug architecture.
Question 4)a) Describe the principle of working of the following:
i) Carry select adder
ii) Barrel shifter
iii) Carry save array multiplier
b) Describe the power distribution and clock distribution in the floor planning.
Question 5)a) Write the data transfer instruction format and give the instruction decoding fields. Also describe the data path activity for LOAD instruction with auto- indexing in a 3 stage pipeline organization using suitable diagrams.
b) Describe the low power system on chip design. Write the architecture for low power.
Question 6)a) For the given function below draw the following: F= (a+b)*(c+d)*(e+f)*(g+h);
i) The data flow graph.
ii) The scheduling and binding of the code.
iii) The final data path.
iv) The controller.
b) With the neat diagram, describe the ARM3 cache memory organization. Give the reason for using 64-way associative CAM-RAM in the design.