Design the footless domino decoder from Exercise 12.5(b) using self-resetting domino gates. Assume the inputs are available in true and complementary form as pulses with a duration of 3 FO4 inverters and can each drive 48 Q of gate width. Indicate transistor sizes and estimate the delay of the decoder.
(a) Estimate the minimum delay of a 10:1024 decoder driving an electrical effort of H = 20 using
(b) footless domino gates