Draw the logic diagram of a four-bit register with four D flip-flops and four 4 X 1 multiplexers with mode selection inputs s1 and s0. The register operates according to he following function table
s1 s0 Register Operation
0 0 No change
0 1 Complement the four outputs
1 0 Clear register to 0 (synchronous with the clock)
1 1 Load parallel data