Suppose a datapath connected to an asynchronous SRAM has control signals addr_sel to select the memory address and d_out_en to enable the memory data tristate drivers. The control section generates these control signals as well as the control signals for the SRAM, as described in Section 5.2.1 and shown in Figure 5.10. Develop a control sequence for a write operation that ensures that the setup and hold constraints are met. How many clock cycles does a write operation take using your control sequence?
