Determine input output impedances and voltage gain of the

Question

Question 1: Design a 3V Zener Diode voltage regulator for a load varies from 0 to 150mW. The input DC supply will vary from 8 to 18 volts. The design should include the power rating of all components. The minimum on current lz_min of the Zener diode must be considered in the design.

a. Comment on you design

b. Repeat the design with load varies from 0 to 6m W. Comment on the new design.

Question 2: For the following Depletion-type MOSFET voltage divider biased circuit with g_os = 30μ5, l_Dss=12mA and Vex-4V.

a. Determine the bias resistors R_s, R₁, and R₂ such that the circuit will have mom than 70% of maximum g_mo and input impedance Z_l > MΩ. Calculate l_DQ, Vgs_Q, and Vds to make sure the circuit is properly biased.

b. Determine input, output impedances, and voltage gain of the circuit, Z_l, Z_o, A_v. Draw the small signal model of the circuit.

d. If the input signal is from -2mV to 2mV, what is the output signal amplitude?

e. What can you do to increase the output signal amplitude by 20%?

Question 3: For the following JFET source follower circuit with g_os = 20μS, l_Dss = 12mA and V_p = -4v

a. Determine the bias resistors R_s, and R_G such that the circuit will be biased at I_d = I_dss/3 and input impedance Z₁,5MΩ. Calculate lac, Vgsc, and Vds to make sure the circuit is properly biased.

b. Determine input, output impedances, and voltage gain of the circuit, Z_i, Z_o, A_v.

c. Draw the small signal model of the circuit.

d. If the input signal is from -20mV to 20mV, what is the output signal amplitude?

e. What can you do to increase the output signal amplitude by 20%?

Question 4: For the following Enhance-type MOSFET teed-back biased circuit with g_os = 30μS. K = 0.3 x 10³ (A/V²) and V_TH = 3V.

a. Determine the bias resistors R₀ and R_f such that the circuit will have g_{m >} 2.0 ms and input impedance Z_i,> 1 MΩ. Calculate l_oQ, VgS_Q, and Vds to make sure the circuit is properly biased.

b. Determine input, output impedances, and voltage gain of the Circuit. Z_I, Z_O, A_v.

c. Draw the small signal model of the circuit.

d. What can you do if you are asked to increase the voltage gain of the circuit?

Question 5: For the following Enhance type MOSFET voltage divider biased circuit with g_os = 30μS, K= 0.3 x 10^-3 (A/V) and V_TH = 3V.

e. Determine the bias resistors R_s, R₁, end R₂ such that the circuit will hare g_a>2.5 mS and input impedance Z_l,>5 MΩ. Calculate I_DQ, Vasa, and Vds to make sure the circu it is properly biased.

f. Determine input, output impedances, and voltage gain of the circuit, Z_I, Z_O, A_V.

g. Draw the small signal model of the circuit.

h. What can you do if you are asked to increase the voltage gain of the circuit?

Question 6: For the following Depletion-type INOSFET self-biased circuit with  g_os = 30μS. I_Dss = 12mA and V_P = -4V.

a. Determine the bias resistors R_s R_G and R_D such that the circuit will have voltage gain more than 10 and input impedance Z_I = 1MΩ. Calculate I_oQ, Vgs_Q, and V_ds to make sure the circuit Is properly biased.

b. Determine input, output impedances, and voltage gain of the circuit, Z_I, Z_O, A_V.

c. Draw the small signal model of the circuit.

d. What can you do if you are asked to increase the voltage gain to 12?