Problem: Select a suitable device among the three provided in the data sheet (NE67400B, NE32984D, NE32584C, NE32484A, NE20200) to design a single stage amplifier to meet the following requirements
Gain (GA) > 15.8 dB
Noise figure (NF) < 0.52 dB
Frequency 10 GHz
VSWRINPUT < 3:1 (Very important this requirement must be meet)
VSWROUTPUT 1:1
(Stability margin)INPUT ≥ 0.2
(Stability margin)OUTPUT ≥ 0.2
1) Analyze the requirements and describe your approach for the amplifier design.
2) Check amplifier stability at the input and output, is the device is not unconditionally stable draw the stability circles on two separate Smith's charts for the input and output planes.
3) For the potential devices, draw the available gain circles in the proper plane.
4) For the potential devices, draw the noise figure circles in the proper plane.
5) Select the device that satisfy the requirements specified above, explain your choice and explain why you pick that device and not the others.
6) For the selected device tune Γs to tradeoff between Gain, noise figure, stability margin and (VSWR) INPUT.
7) Select the optimum value for the input Γs accordingly to the amplifier specifications and stability requirements. Pay particular attention to the VSWRIN requirement and make sure you meet this specification. Calculate the correspondent value of ΓL and verify the stability requirements for it in the proper plane.
8) Use the Smith chart to design the input, output, matching networks, use balanced open stubs with 50 ohms characteristic impedance in combination with TLs.
9) Realize your matching circuits in MIC technology with microstrip lines. Use RT-Duroid as substrate (εr=4.0, h=1.3 mm) and 402 form factor passive components for the bias circuit. (Use the attached figures)
10) Design the bias network for the device including as follows:
- Use High impedance quarter wave stub configuration to provide the bias to the gate and drain of the device, the source should be connected to ground trough a via hole.
- Assume differential voltage +5V/-5V supply is available for the bias of the device.
- You can assume no current on the gate (IG~0) of the device when biasing the gate (VGS).
- Use the I-V curve in the data sheet and draw the proper load line to calculate the resistors needed to bias the drain (VDS).
- Compute the values for the choke inductors
11) Provide a good draw to scale of the circuit layout including matching network, and bias network.
12) Summarize your final amplifier circuit and performance trade off.
13) If your design cannot meet all the requirements explain why, discuss what you learn during this project and explain your tradeoffs.
Attachment:- Final Project.rar