(a) Write VHDL for an 8-bit MISR that is similar to Figure 10-28.
(b) Design a self-test circuit, similar to Figure 10-25, for a 6116 static RAM (see Figure 8-15). The write-data generator should store data in the following sequence: 00000000, 10000000, 11000000, ..., 11111111, 01111111, 00111111, ..., 00000000.
(c) Write VHDL code to test your design. Simulate the system for at least one example with no errors, one error, two errors, and three errors.
