Consider the system in Figure CP10.1, where
Design a compensator Gc(s) so that the steady-state tracking error to a ramp input is zero and the settling time (with a 2% criterion) is less than 5 seconds. Obtain the response of the closed-loop system to the input R(s) = 1/s2 and verify that the settling time requirement has been satisfied and that the steady state error is zero.
