Design a 16 bit adder using both the ripple carry and CLA methods. Use 4-bit CLA blocks for the carry-lookahead design. Use only two-input logic gates in your design. Simulate the design using LogiSim at the logic gate level.
Assume that each two-input gate occupies 10 µm2 , has 20 ps delay, and has 15 fF of total capacitance.
i. Compare the area, delay, and power of the adders when operating at 200 MHz with a 1.2 V supply
ii. Discuss the tradeoffs in power, area, and delay