Problem: Derive the small-signal voltage gain of an inverter as the input voltage sweeps from 0 to VDD We assume that VDD > Vtn + |Vtp|. Express your answer using small signal parameters. As the input voltage sweeps from 0 to VDD, the PMOS and NMOS transistors are biased at different operation regions, at which region do we get the highest voltage gain? For simplicity, when VGS