Assignment
1. Given the following cache specifications: (S, E, B, m) = (4, 2, 2, 6) where S is the number of sets, E is the number of lines per set, B is the number of blocks per line, and m is the memory address length.
a. Construct a block diagram of the cache.
b. Identify the tag bits, set bits and block offset bits for the address field.
c. The cache replacement policy is: Last-in First-out.
Step 1: Initial State
Define the initial structure and state of the cache as done in class. The # of rows in the table below must be changed to fit your cache model.
|
Set
|
Line
|
Valid
|
Tag
|
Block 0
|
Block 1
|
Step 2: Read Address 0
Show how the cache contents change as the processer requests data from the following memory locations: 0, 32, 17, 33, 22, 9. Comment whether you have a cache hit/miss after each read.
Data at Address x is referred to as m[x]
If a cache line has to be overwritten, cross out the old line and write the new one or draw a new table.
2. Repeat Q1 for the following cache specifications: (S, E, B, m) = (4, 1, 4, 6)
The response should include a reference list. Double-space, using Times New Roman 12 pnt font, one-inch margins, and APA style of writing and citations.