2. We have a RISC architecture with three stage pipelining.
I: Instruction fetch.
E: Execute. ALU execution OR Calculates memory address
D: Memory. Register-to-memory or memory-to-register operation.
Considering the operation of the following five statements:
LDA rA, AdrM1 ; load register rA with Memory content from address AdrM1
INC rB ; increment register rB
JMP AdrX ; Branch (Jump) at statement from address AdrX
ADD rC,rD ; Add the register rC with register rD and hold the result in register C3
DCR rD ; Decrement register r6
......
AdrX: LDA AdrM2, rC ; load Memory from address AdrM1 with content of register rC
Draw the timing for:
a) Normal Branch
b) Delayed Branch
c) Optimized Delayed Branch
Normal Branch (JMP imply pipeline must be cleared of instruction ADD )
Instructions T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
LDA rA, AdrM1 I E D
INC rB I E
JMP AdrX
ADD rC,rD
Instruction from address AdrX
LDA AdrM2, rC
Delayed Branch
Instructions T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
LDA rA, AdrM1 I E D
INC rB I E
Fill in
Fill in
Instruction from address AdrX
LDA AdrM2, rC
Optimized Delayed Branch
Instructions T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
LDA rA, AdrM1 I E D
Fill in
Fill in
Instruction from address AdrX
LDA AdrM2, rC