Consider the read operation of the 6T SRAM cell of Fig. when it is storing a 0, that is, VQ =0 V, and VQ =VDD. Assume that the bit lines are precharged to VDD before the word-line voltage is raised to VDD. Sketch the relevant part of the circuit and describe the operation. Show that the analysis parallels that presented in the text for the read-1 operation.
