Consider the nmos r-s flip-flop in figure -determine the

Question

Consider the NMOS R-S flip-flop in Figure biased at V_DD = 2.5 V.

The threshold voltages are 0.4 V (enhancement-mode devices) and -0.6 V (depletion-mode devices). The conduction parameters are K₃ = K₆ = 40μA/V², K₂ = K₅ = 100μA/V², and K₁ = K₄ = 150μA/V².

If Q = logic 0 and  = logic 1 initially, determine the voltage at S that will cause the flip-flop to change states.