Consider the NMOS R-S flip-flop in Figure biased at VDD = 2.5 V.
The threshold voltages are 0.4 V (enhancement-mode devices) and -0.6 V (depletion-mode devices). The conduction parameters are K3 = K6 = 40μA/V2, K2 = K5 = 100μA/V2, and K1 = K4 = 150μA/V2.
If Q = logic 0 and
= logic 1 initially, determine the voltage at S that will cause the flip-flop to change states.
![2328_Fig 2.jpg](https://secure.tutorsglobe.com/CMSImages/2328_Fig 2.jpg)