Consider the CMOS RAM cell and data lines in Figure biased at VDD = 2.5 V.
Assume transistor parameters 
= 80μA/V2, 
= 35μA/V2, VT N = 0.4 V, VT P = -0.4 V, W/L = 2 (MN1 and MN2), W/L = 4 (MP1 and MP2), and W/L = 1 (all other transistors). If Q = 0 and 
= 1, determine the steady-state values of D and 
after the row has been selected. Neglect the body effect.
