Consider the cmos ram cell and data lines in figure -, Electrical Engineering

Consider the cmos ram cell and data lines in figure -

Consider the CMOS RAM cell and data lines in Figure biased at V_DD = 2.5 V.

Assume transistor parameters = 80μA/V², = 35μA/V², V_{T N} = 0.4 V, V_{T P} = -0.4 V, W/L = 2 (M_N1 and M_N2), W/L = 4 (M_P1 and M_P2), and W/L = 1 (all other transistors). If Q = 0 and = 1, determine the steady-state values of D and after the row has been selected. Neglect the body effect.

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Electrical Engineering: Consider the cmos ram cell and data lines in figure -

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