Consider a VLSI chip with 100,000 gates and 2000 flip flops. A combinational ATPG program produces 500 vectors to fully test thelogic. Find the minimum number of scan test cycles if 20 scanchains are implemented. Given that the circuit has 20 primary inputand 20 primary output data pins and only one extra pin availablefor test ,how much overhead will be needed for the new design?