Consider a paging architecture with a logical address space of 256 pages with a 256 byte page size, mapped onto a physical memory of 64 frames. Assume that it takes 50ns to access a memory page, and TLB lookup time is 2ns.
- How many bits are required in the logical address and how much virtual memory can a process on this machine address?
- How many bits are required in the physical address and how much physical memory can an OS on this machine use?
- What is the optimal number of hierarchical page table levels would you recommend for this architecture (assume that each PTE requires 2 bits to store the valid and protection bits).
- How long does a paged memory reference take in case of a TLB miss? If the TLB has a 0.9 hitrate, what is the effective access time?