Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capacitance etween the output node and ground. Compare the values of tPLH and tPHL, obtained when the devices are sized as in Fig. to the values obtained when all n-channel devices have W/L = n and all p-channel devices have W/L = p.
![994_node.png](https://secure.tutorsglobe.com/CMSImages/994_node.png)