1) Specify the data types specified in VHDL.
2) Explain the term delta delay?
3) Write down the syntax for the wait statement.
4) Explain what is component instantiation? Provide an example.
5) Explain what is meant by the guarded signals?
6) Explain the need for the configuration?
7) Explain what is meant by the package? Provide an example.
8) Specify the design units in the Library file.
9) Explain what is meant by an identifier?
10) Write down few conditional statements in the verilog HDL.