For the given SM chart:
(a) Complete the following timing diagram (assume that X1 = 1, X2 = 0, X3 = 0, X5 = 1, and X4 is as shown). Flip-flops change state on falling edge of clock.
(b) Using the given one-hot state assignment, derive the minimum next state and output equations by inspection of the SM chart.
(c) Write a VHDL description of the digital system.