Briefly discuss 1 paragraph the impact trade offs of the

Question

Minor corrections:

P1. c: assume for this part that the inverter trip points are at Vbatt/2

P1. f: incorporate the impact of Rin, Cc and Rs in this transfer function

P1. g: your design should absorb the effects of Cc, Rin and Rs.

P3: set VDD=2.5V (not 2V)

P3c: in terms of "N"

P3f: use the same gm, ro as in "c"

P3g: is this a robust design? If not, why not (one sentence)

P4: assume the clock has 2 phases, φ1, φ2

Question 1: The LC buck converter circuit shown takes in a DC voltage V_in, which combines with an AC-coupled triangle wave with peak-to-peak amplitude V_tri, and period T, and then is thresholded by a string of inverters before driving an LC load.

a. Briefly discuss (1 paragraph) the impact/ trade offs of the various components in the circuit. In particular, discuss briefly how the values of L, C_L, C_c, R_in, the sizing of the 3 inverters, T, and the ratio V_tri/V_batt impact: input range, efficiency, and ripple.

The small-signal transfer function (assuming <<√LC_L) is:

Vout/V_in = V_batt/V_tri. (1/(1+ (s/Qω_n) + (s/Qω_n)²)). (1 + (s/z))/(1 + (s/p))

b. Relate ω_n, Q, p and z to L, C_r, R_in, R_tri, C_c, R_L (the parasitic resistance of the inductor ) the output conductance of a unit inverter g_dsinv and the sizing of the 3 inverters.

ω_n= rad/s, Q=
P = rad/s, z= rad/s,

c. Sketch V₁-V₄, I_L and V_out for V_batt = 3V, V_tri = 2V, V_in = 1V, (assuming << √(LC_L) and also assuming I_DCout > L.T.V_batt).

d. Assuming the inverters are sized so that k = μc_ox W/L is the same for N-and Pfets (so, for the same I_D, the have the same V_od), what is the range of Vin that provides linear control of v_out, in terms of V_batt, V_THN and V_THP?

Now, we will want to design a feedback circuit, taking in V_out and a voltage V_ref and generating such that when the loop is closed V_out=V_ref to within 1%.

e. Based on the transfer function in (b), what must the feedback DC gain be to achieve 1% accuracy? What, approximately, is the maximum closed-loop bandwidth (essentially UGBW) that can be achieved while still having a reliably stable design? Provide your answers in terms of the coefficients in part (b): ω_n, Q, p and z.

H(0)= BW=

f. Design a feedback transfer function, H(s) that provides a closed loop behavior with the desired gain and a bandwidth that approaches the above limit within a factor of 10. Write the coefficients of that transfer function in terms of the coefficients in part (b)
H(s) =

g. Design a circuit to implement the above transfer function. Assume transistors with unit g_m = 100μS, unit r₀=200kΩ) for V_od = 200mV, I_d=10μA, V_TH=0.4V. Design for ω_n=10Mrad/s, Q=10, V_batt=3V, V_tri,=2V and Rs=10kΩ. You may choose C_c, and R_in (or incorporate R_in, into the output resistance of your circuit). Critically: the circuit must support an output (V_in) range of 0.5 to 2.5V, and input ("Vout" and Vref) range from 1 to 2V and implement the transfer function from (f) without significantly degrading phase margin of the loop as a whole. Draw the schematic of the circuit, with multiplicities and give the values of any explicit resistors and capacitors, including C_c and R_in.

Question 2:

A 3-stage inveter-style op-amp.

a. For the circuit shown, write the transfer functions V_out/V_in+ and V_out/V_in- in terms of the inverter unit input capacitance, C_inv, transconductance, G_inv, output resistance, Roniv, multiplicities N₁, N₂, N₃, and load R_L and C_L. Assume the inputs are biased at the trip-point of the inverters (where V_in=V_out). Also, rewrite these transfer functions in terms of differential and common mode inputs.

V_out/V_in^- =
V_out/V_in⁺ =
V_out/V_indiff =
V_out/V_inCM =

b. Estimate the differential input referred thermal noise (assume effective y = 1 for an inverter). Which inverters you expect to dominate noise? What is the (approximate) noise in terms of 4kT, unit Gminv, Roinv and N1-N3?

Which components matter?

V_ndiff²/HZ=

c. How would you choose N1, N2 and N3 based on input referred noise, RL (for rail-to-rail output), and minimizing current consumption. Describe in words (1 paragraph), supported by equations.

Now, the amplifier is compensated as shown.

d. Compute the dominant pole and zero at the node between the 2^nd and 3^rd stages (V₂) in terms of C₂, N₂, N₃, C_L, R_L, G_minv and R_oinv.

Assume C₂>> N₃C_inv, and R₂→0. Sketch the Bode plot of the transfer functions V₂/V₁ and V_out/V₁ and lable magnitudes and break frequencies. Hint: this is Miller compensation, so use that style of analysis when figuring out poles and zeros.

p2 =

z2 =

e. Similarly, compute the dominant pole and zero at the node between the 1^st and 2_nd stages, in terms of N₁, C₁, G_minv, R_oinv and the pole (p₂) from, the previous section. Sketch the Bode plot of the transfer functions V₁/V_in and V_out/V_in. For simplicity treat the Feedback inverter as an ideal amplifier with gain = G_minR_oinv, and low output impedance.

f. What purpose does putting R₂ in series with C₂ serve? Why is there no need for a resistor in series with C₁?

g. What benefits does using the feedback inverter provide (list 3 benefits) and why might using it be hard in practice?

Question 3: For the amplifier shown:

a. What are the DC bias points (node voltages) of the circuit? Assume V_od=0.2V, V_THN=0.4V, V_THP = 0.5V and V_DD=2V. Write your answers in terms of Vinal.

V_a= , V_b= , V_c= , V_d= , V_e=
V_g= , V_h= , V_outcm=

b. Which transistors act as the following subcomponents:
Differential pair:___
Passive mirror:___
Active mirror:___
Cascode:___
CMFB:___

c. What is the small signal gain of the amplifier shown.? Assume unit g_m = 100μS, r_o=400kΩ:

A_DC=

d. Which components can you ignore when computing noise, and why?

e. What is the input-referred thermal noise, in terms of kT, N and unit gm (assume y=1)

V_in²/Hz = ___

f. What must N be for the input referred noise to be 2nV/Hz^1/2?

N = _____

g. For process variation where, V_THN and V_THP vary independently by +/- 100mV (but l_bias and V_od are constant) what is the input common mode range that keeps all transistors out of triode across all process corners? For each extreme, state which transistor will enter triode first, and under what process corner.

_____

h. If individual component mismatch in V_TH is σΔ_VTH = 8mVμm/(W.L)^1/2. What 3-sigma variation in input-referred DC offset can you expect, as a function of N? Assume unit nfets have W/L are 4µm/1µm , and unit pfets have W/L are 16µm/ 1µm

3σV_in =

i. Bonus: Applying the same mismatch what 3-sigma variation do you expect in I_N? In I_p? What 3-sigma variation do you expect in I_casc.. What is the maximum N allowable that guarantees circuit function under 3-sigma corners of mismatch?

N < _____

Question 4: Open ended design : design, at a transistor level, a circuit that provides a 1.2V (accurate to 50mV) output, able to source up to 50 μA with less than 50mV of droop (so, a 1 kΩ resistance), when powered by a 0.4V supply (typical for a single silicon photovoltaic). Assume transistors with k=μc_ox = 1mA/V², g_mr_o = 40.

Assume you have access to a 1MHz clock and a level shifter to set its amplitude to and VDD you can generate. Provide a circuit topology that could reasonably be fully integrated (so, no inductors) and provide critical component values (R's, C's and W/L) as well as critical sizing ratios between transistors, capacitors and/or diodes. Your final schematic must be neat, have different sub-blocks clearly labelled and either clearly indicate component values, or else label each component and have a table listing values.

You may also include 1-2 paragraphs describing your design and reasoning, to increase my chance of understanding/appreciating what you have done. Points will be awarded for functional designs. Bonus points for minimizing current from the 0.4V supply, and for minimum size (based on W,L of large devices, Capacitor values and Resistor values, assuming L_min=0.25um, w_min of resistors=0.25um, and ρ = 1kΩ/square, and Co = 2fF/μm²). No bonus points if you compute power or area wrong by more than 10%.

IDD = ___μA, Area = ___μm²