Assume that only 2-input nand nor xor and xnor gates are

Question

(Counter Design) Design a 2-bit counter that behaves according to the two control inputs I₀ and I₁ as follows: I₀, I₁ = 0, 0: stop counting; I₀, I₁ = 0, 1: count up by one; I₀, I₁ = 1, 0: count down by one; I₀, I₁ = 1, 1: count by two.

(a) Draw the state diagram and state transition table.

(b) Implement the counter using D flip-flops.

(c) Assume that only 2-input NAND, NOR, XOR, and XNOR gates are available. Draw the schematic for your minimum gate count implementation.