1. What is the optimal block size for a miss latency of 20×B cycles?
2. What is the optimal block size for a miss latency of 24+B cycles?
3. For constant miss latency, what is the optimal block size?
4. In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, P1 and P2.
