Assume gate delays of 1ns, bus propagation delay of 2ns, latch propagetionn delay of 3ns. Assume unlimited gate fan-in and fan-out. Latch delay includes setup,hold and minimum pulse width times. How long does it take for the control signal to become valid at the output of the control unit from the time of the rising edge of the T control step signal. Assume control unit delay of 6ns. what is the minimum clock period for step T3