Assume 64-bit addresses and the layout from chapter 4 how, Computer Engineering

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Assume 64-bit addresses and the layout from chapter 4 how

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1. Consider a 4-way set-associative cache with 64-byte data lines and 4096 entries. Assume 64-bit addresses and the layout from chapter 4. How many bits would the tag field be in this case?

2. Putting a 4 in the MAR and starting a memory write, would write to which bytes?

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Computer Engineering: Assume 64-bit addresses and the layout from chapter 4 how

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Computer Engineering: Assume 64-bit addresses and the layout from chapter 4 how

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