Architecture for the 4-bit comparator


Question 1: Design a 2 to 4 decoder circuit. Provide its entity declaration and structural model and behavioral model. As well draw the waveform providing relation between its inputs and outputs.

Question 2: Write brief note on the difference between if and case statement.

Question 3: Write brief note on the Loop statement.

Question 4: Write brief note on the Next statement.

Question 5: Write down truth table, working behavioral/dataflow architecture for the Code convertor. As well draw the circuit and output waveform.

Question 6: Write down truth table, working behavioral/dataflow architecture for the 4-bit comparator. As well draw the circuit and output waveform.

Question 7: Write down truth table, VHDL Code for the n-bit register with parallel load. As well draw the circuit and the output waveform.

Question 8: Write down truth table, VHDL Code for the J-K flip flop by using behavioral modeling.

Question 9: What are fundamental components of computer? Write down the VHDL code for memory subsystem.

Question 10: Write brief note on the FPGA. 

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Electrical Engineering: Architecture for the 4-bit comparator
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