Repeat Exercise 7.77 for the asymmetric BUT flop in Figure X7.78.
Exercise 7.77
A BUT flop may be constructed from an NBUT gate as shown in Figure X7 .77. (An NBUT gate is simply a BUT gate with inverted outputs; see for the definition of a BUT gate.) Analyze the BUT flop as a feedback sequential circuit and obtain excitation equations, transition table, and flow table. Is this circuit good for anything, or is it a flop?
